A semiconductor chip is an array of devices with conducting terminals that are interconnected by wiring patterns of metal strips. In Very Large Scale Integration (VLSI) chips, these metal wiring patterns are multilayered. Each wiring layer is separated from other conducting layers by layers of insulating material. Interconnections between different wiring layers are made by through holes (vias) that are etched through the insulating material layers.
As VLSI chip features shrink and the number of wiring layers increases, surface irregularities in each layer translate to subsequent layers, making each subsequent layer's surface even more irregular. These irregularities distort shapes formed on the surface, making level-to-level alignment difficult. In some cases, this distortion is so severe as to make it nearly impossible to adequately replicate (print) the intended shape or align printing masks to previous levels. One way surface irregularities were reduced was to fill the vias with conductive material (i.e., from studs in the vias) before printing the wiring pattern. However, the raised wire shapes still left caused irregularities in subsequent layers' surfaces. Therefore, techniques have been developed that are used at various levels to create a nearly perfectly flat or planar surface in order to achieve high dimensional and geometric accuracy. These techniques are known, in the art, as planarization.
One such planarization process is Chemical-Mechanical Polishing, also known as Chem-Mech Polishing or CMP. CMP involves applying an abrasive in a solution (known as a slurry) to the wafer surface and, then, polishing the surface. Additives in the solution chemically react with the surface material, softening it, and, then, the highest features in the softened surface are removed by the abrasive particles.
When the layer to be polished is a uniform material with an irregular surface topography, CMP is a relatively simple process. Thus, CMP is widely used in the prior art to planarize insulating dielectrics in the top most semiconductor chip layers, i.e, those closest to the chip's upper surface. These top most layers are sometimes called Back End Of the Line (BEOL) layers, likening to the semiconductor chip manufacturing process to an assembly line where these steps occur at the back of the line. Likewise, early processing steps are at Front End Of the Line (FEOL) and early layers are FEOL layers; middle steps/layers are Middle Of the Line (MOL).
CMP also is used to form studs in interlevel vias through an already planarized dielectric layers between conducting layers such as between two wiring layers. To form studs: first, the dielectric layer is planarized using CMP; next, the via pattern is opened through the dielectric layer; a layer of conducting material, such as polysilicon (also referred to as `poly`) or tungsten, is formed over the patterned dielectric; and, finally, the layer of conducting material is polished down to the dielectric layer so that the conducting material remains only in the vias.
Unfortunately, after CMP, scratches may remain in the polished dielectric layer. Further, the polishing step may have failed to remove 100% of the surface irregularities caused by underlying layers. Further, because of depressions left in the surface, CMP may not have to remove all unwanted conducting material. Finally, each polishing step introduces some non-uniformity in the polished layer. These shortcomings may cause chip defects, e.g., leakages and shorts, surface irregularities, and non-uniform dielectric. Furthermore, CMP stud formation is a time consuming process.